IntelliSense Total MEMS Solutions: Design, Prototyping and Foundry Services for Asia and the World
Semiconductor foundries, such as Taiwan Semiconductor Manufacturing Company (TSMC) in Taiwan, have become an integral part of the ecosystem surrounding ‘fabless’ electronics companies producing large volume integrated circuits (ICs). This paradigm traditionally exploited the partitioning of the design and fabrication disciplines, as well as the economies of scale enabled by a dedicated fabrication facility utilising common processes to mass produce a variety of end ICs. Similarly, the ecosystem of...
IntelliSuite v8.8 Relea...
PRESS RELEASE Woburn, MA – February 3, 2014 – Today, IntelliSense announced a major release of its industry-leading software tools for the MEMS community, IntelliSuite v8.8. The new IntelliSuite version includes major updates for all software modules and the addition of a new tool,...
Webinar: System Level A...
Topic: System Level Analysis and Simulation for MEMS Date: October 31st, 2012 Time:1:00 pm – 2:00 pm (EDT) Presenter:Tom Hall Abstract – IntelliSuite was the first MEMS-specific CAD tool and has been under active development for over 20 years. This webinar will explore how SYNPLE,...
IntelliSense MEMS Press...
IntelliSense’s hardware team has developed a series of MEMS pressure sensors and fabricated them in our Nanjing, China facility. The sensors are available packaged or unpackaged, and further custom development can be done upon request. For more information, check out the...
IntelliSuite v8.7 Relea...
PRESS RELEASE Woburn, MA – February 6, 2012 – Today IntelliSense announced a major new version of its market-leading software for the MEMS industry, IntelliSuite v8.7. IntelliSuite v8.7 includes upgrades to almost every module of IntelliSuite and introduces several...
Design Rule Checking
Performing a design rule check is a very important step in the MEMS design cycle. Check out the video below to see how Design Rule Checking is performed on a MEMS layout, in this case within Blueprint: DRC in action with...
Efficient optimization ...
Genemala Haobijam·Roy Paily Abstract: In this paper we present an efficient method of determining the optimized layout of on chip spiral inductor. The method initially identifies the feasible region of optimization by developing layout design parameter bound curves for a large range of...
Design of multilevel py...
Genemala Haobijam·Roy Paily Abstract: This paper presents the design of a multilevel pyramidically wound symmetric (MPS) inductor structure. Being multilevel, the MPS inductor achieves high inductance to area ratio and hence occupies smaller silicon area. The symmetric inductor is...